Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

Filter

My recent searches
Filter by:
Budget
to
to
to
Skills
Languages
    Job State
    174 jobs found, pricing in NZD

    Discuss with me to get more details on this task. Only person who has worked on FMCJESDADC1 should bid.

    $321 (Avg Bid)
    $321 Avg Bid
    2 bids

    Write a simple verilog code to create dynamic lighting using led. see the attached files and respond

    $181 (Avg Bid)
    $181 Avg Bid
    21 bids

    know Verilog code, how how to use Quartus and FPGA board.

    $36 (Avg Bid)
    $36 Avg Bid
    14 bids
    Program a microcontroller 3 days left
    VERIFIED

    need you to program a micro controller as per my requirement

    $32 (Avg Bid)
    $32 Avg Bid
    17 bids
    Project for Loi L. 6 days left
    VERIFIED

    Hi Loi L., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $153 (Avg Bid)
    $153 Avg Bid
    3 bids

    It is to Implement a 16-bit CORDIC Computer. The design to be implemented is based on a bit-serial configuration. It will take as input a 16-bit signed binary fixed point number, corresponding to an angle in the range 0 to π/2, and use the CORDIC method to find the sine and cosine of this angle. This will be coded in Verilog and implemented on the Basis 3 board.

    $243 (Avg Bid)
    $243 Avg Bid
    3 bids

    I want to hire a person which having the knowledge of matlab and simulink, and design the mppt algorithm associated with my idea. Also the person should have the knowledge of electrical like DC-DC converter, basic concept of solar cell, maximum power point algorithm.

    $199 (Avg Bid)
    $199 Avg Bid
    22 bids

    Inroduction: This project is about designing and simulating a clock-driven quad-processor scheduler in an object-oriented manner. The scheduler consists of a multi-level job queue where each level follows a different scheduling algorithm viz. Priority, Shortest Job First (SJF) and First-come-first-serve (FCFS). These queues will be enqueued with PCBs. The PCBs can further be classified into Rec...

    $30 / hr (Avg Bid)
    $30 / hr Avg Bid
    5 bids
    $177 Avg Bid
    9 bids
    robust control project 1 day left
    VERIFIED

    design a control system using matlab or simulink

    $67 (Avg Bid)
    $67 Avg Bid
    15 bids
    model in simulink 1 day left
    VERIFIED

    i have model for one user i want update to 5 user and get some results

    $535 (Avg Bid)
    $535 Avg Bid
    10 bids

    Help me to design the circuit attatched and find out the unkown parameters both

    $47 / hr (Avg Bid)
    $47 / hr Avg Bid
    20 bids

    Please, see the attached file. Analysis and design combinational and sequential digital logic, modeling concurrent digital systems using VHDL and Analogue filter.

    $290 (Avg Bid)
    $290 Avg Bid
    18 bids

    hi i want someone to connect the function generator and the scope in multisim of electric circuit thank you

    $33 (Avg Bid)
    $33 Avg Bid
    9 bids
    Simulink to VHDL 4h left
    VERIFIED

    I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time.

    $33 (Avg Bid)
    $33 Avg Bid
    5 bids

    Hi, Need the completed project in 36 hours. Share the codes in 24 hours and the report in 36 hours. Project details are attached here. Sample codes are attached in the files. You need to use the similar codes for the work

    $143 (Avg Bid)
    $143 Avg Bid
    3 bids

    I have .vhdl files for an implementation of google chrome's 'dino run' which appears when the user has no wifi connection. However, I would like to have the same functionality with Verilog description language.

    $171 (Avg Bid)
    $171 Avg Bid
    9 bids

    I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers.

    $78 (Avg Bid)
    $78 Avg Bid
    7 bids

    I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers.

    $65 (Avg Bid)
    $65 Avg Bid
    3 bids

    I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers.

    $50 (Avg Bid)
    $50 Avg Bid
    2 bids