Verilog / VHDL Jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    27 jobs found, pricing in NZD

    I have some tasks related to computer architecture. I want someone who is an expert in VHDL.

    $18 / hr (Avg Bid)
    $18 / hr Avg Bid
    1 bids

    I have some tasks related to computer architecture. I want someone who is an expert in VHDL.

    $4 / hr (Avg Bid)
    $4 / hr Avg Bid
    1 bids

    Program microcontrollers and provide code for cloning and or copy process etc.

    $1489 (Avg Bid)
    $1489 Avg Bid
    11 bids
    VHDL/Verilog Project -- 3 6 days left
    VERIFIED

    Please message me for more details. For this project, I will send you zip fie that has all information.

    $30 (Avg Bid)
    $30 Avg Bid
    4 bids

    hello I need help in a project on a computer architecture ,mips, arm , LEGv8

    $82 (Avg Bid)
    $82 Avg Bid
    1 bids

    Hi Looking for person who can support work from office or concern that can contract people to work for projects ( test bench development/ requirements writing / development and implementation tests/ simulation/ function coverage ) UVM / SYSTEM VERILOG must.

    $10 / hr (Avg Bid)
    $10 / hr Avg Bid
    1 bids

    MIPS programming expert needed

    $25 (Avg Bid)
    $25 Avg Bid
    1 bids

    I have a project on mips and LEGv8 and need help

    $37 (Avg Bid)
    $37 Avg Bid
    1 bids

    MIPS instructions and simple Assembly

    $15 - $45
    Sealed
    $15 - $45
    2 bids

    The EE 272 Simple Neural Evaluation engine takes weights for a neural network, and applies them to input data. The design is flexible, and assumes very little about the neural network. This design assumes all data is contiguous and all weights are processed. The design assumes the input data is 24 bits per sample in 2’s complement form. For math reasons, the input number are commonly scaled to be between -1 and +1. This implies the data is actually 8.24 binary fixed point. This scaling is important when processing weights. The weights are assumed to be in 8.24 form. (32 bits fixed binary point) The neural network can have up to 4096 inputs per layer, and this adds 12 additional bits to the sum. There can be up to 4096 nodes per layer. The input data is mapped to 8.24 before operation...

    $45 (Avg Bid)
    $45 Avg Bid
    1 bids

    The EE 272 Simple Neural Evaluation engine takes weights for a neural network, and applies them to input data. The design is flexible and assumes very little about the neural network. This design assumes all data is contiguous and all weights are processed. The design assumes the input data is 24 bits per sample in 2’s complement form. For math reasons, the input number are commonly scaled to be between -1 and +1. This implies the data is actually 8.24 binary fixed point. This scaling is important when processing weights. The weights are assumed to be in 8.24 form. (32 bits fixed binary point) The neural network can have up to 4096 inputs per layer, and this adds 12 additional bits to the sum. There can be up to 4096 nodes per layer. The input data is mapped to 8.24 before operation...

    $45 (Avg Bid)
    $45 Avg Bid
    1 bids

    Need someone who is experts in MIPS

    $30 (Avg Bid)
    $30 Avg Bid
    1 bids
    verilog coding using ModelSim 5 days left
    VERIFIED

    looking for some help with my verilog coding project using ModelSim. please bid if you can

    $51 - $69
    Sealed
    $51 - $69
    4 bids

    I need this mini project in VHDL with all displayed on display. YouTube link is there for calculator help to understand. According to that program it.

    $257 (Avg Bid)
    $257 Avg Bid
    2 bids

    waste segregation conveyor with metal detector and moisture sensor simulation using proteus

    $21 (Avg Bid)
    $21 Avg Bid
    2 bids

    Need someone good expert in computer architecture In this project, you will be implementing a pipelined MIPS processor datapath with the following features: 1) FDEMW 5-stage pipeline with branch resolution in D. Non-memory hazard detection in D. a) 2-cycle pipelined multiplication unit spanning E and M stages: Reads inputs in E, produces outputs in M (available in W)

    $12 - $30
    $12 - $30
    0 bids

    Multiplication and addition of two 16 bit numbers with various resource constraints. Below is the expression : Y= x0h0+x1h1+x2h2.........x0h9. You should perform the above in a specific manner in VHDL code . For more detail find the attached file.

    $225 (Avg Bid)
    $225 Avg Bid
    2 bids

    i am working on project where i have to generate same sort of shock that normally shock book park generates. please let me know if you can help me with that.

    $246 (Avg Bid)
    $246 Avg Bid
    8 bids
    MIPS processor datapath 4 days left
    VERIFIED

    Need someone who is experts in MIPS

    $111 (Avg Bid)
    $111 Avg Bid
    4 bids

    Hey, I am looking to implement a carry-save adder in System verilog

    $37 (Avg Bid)
    $37 Avg Bid
    7 bids

    I need help programming a microcontroller (PIC16LF1902-I/SS). The micros job is to count the duration of a momentary switch being activated, and compare that time to the stored highest time previously reached on that device. The output screen is a GDC0209 ( , ) The switch is a vibration sensor. I need to current draw to be 400uA when the device is running and displaying the time. Attached is the functional requirements. Please ask me whatever questions you have

    $577 (Avg Bid)
    $577 Avg Bid
    26 bids

    Two 16-bit number from X0 and X9 and H0 to H9 multiply them and add them . Code shall be done in VHDL Y= x0h0+x1h1+x2h2+x3h3+........x9h9. For more details find the attached Set of Question.

    $168 (Avg Bid)
    $168 Avg Bid
    4 bids
    orCAD Software Expert 1 day left
    VERIFIED

    Task1: An audio signal processor has to attenuate a specific range of frequencies in the specified stop band and allowing the frequencies to pass outside the stop band. Design a prototype 4th order active band stop filter and 6th order active band stop filter using Butterworth filter for a desirable resonant frequency and bandwidth as per the given block diagram representation. Task2: In a combinational logic circuit the decoded output depends on the specified combination of bits at the data input. 1) The simulation design should be done for the combinational logic circuit such that it has three input lines and eight output lines. 2) Develop a truth table and the logic symbol for the combinational logic circuit designed.

    $47 (Avg Bid)
    $47 Avg Bid
    1 bids
    Circuit design 1 day left

    Need a circuit integrating multiple simple circuits

    $538 (Avg Bid)
    $538 Avg Bid
    17 bids

    To whom it may concern, I'm looking for someone experienced who can develop a basic calculator using verilog on vivado with specific requirements in a short period of time. If you think this fits your skills, let me know and lets discuss things further!

    $36 (Avg Bid)
    $36 Avg Bid
    9 bids
    Dc motor pwm , vhdl using fpga 6 hours left
    VERIFIED

    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite)

    $47 (Avg Bid)
    $47 Avg Bid
    5 bids

    Proyecto de circuito en Logisim

    $145 (Avg Bid)
    $145 Avg Bid
    5 bids