Asic design - Verilog/HDL code -Design -- 2

Cancelled Posted 7 years ago Paid on delivery

$30-250 USD

Paid on delivery

Cancelled Paid on delivery

Analyze, design, synthesize, and simulate logic circuits using Verilog-HDL and different

widely-used tools such as ModelSim

Verilog / VHDL

Project ID: #14010647

About the project

9 proposals Remote project Active 7 years ago

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9 freelancers are bidding on average $159 for this job

raulbehl's Profile Picture
raulbehl

Hello! I am an experienced Engineer and have been helping out many on this platform. It would be great if I could help you out. Thank you!

$155 USD in 3 days
(63 Reviews)
5.9
jambakhtiar's Profile Picture
jambakhtiar

Hi, How are you. I saw you job. And I'm interested to do it. Let me know if you are willing to work with me.

$200 USD in 6 days
(4 Reviews)
1.5
elamirin's Profile Picture
elamirin

Hi, I am working as an IC Digital Designer consultant since about 10 years now. So I have a strong background in ASIC and FPGA design flow from RTL to GDSII. We can have a first contact to discuss about your needs and More

$222 USD in 5 days
(0 Reviews)
0.0
weld3li's Profile Picture
weld3li

Hello, I can do this job for free :) Please give me more informations to start about the system you want to implement and i will send you my reply asap, Thank you kind regards

$30 USD in 10 days
(0 Reviews)
0.0
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