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It's currently 3:02 PM here
Joined September 15, 2015
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Raghumanohar A.

@raghumanohar

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Verilog Designer, Technical writer

Design engineer at sarvasya semiconductors, involved in IP core designing and Image processing solutions

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Experience

Design Engineer

SARVASYA Semiconductors
Feb 2015 - Present
Design engineer at sarvasya semiconductors involved in IP core designing

Education

M.Tech (VLSI Design & Embedded systems)

Visvesvaraya Technological University, India 2014 - 2015
(1 year)

Publications

Design and implementation of 64-bit KSA

IJEETC
Technical Research paper on design and implementation of high speed novel 64-bit Kogge stone Adder

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