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UDP data filtering using Xilinx Zynq 7000 family Socs

8 freelancers are bidding on average $1278 for this job

$1250 USD in 20 days
(85 Reviews)
6.2
ducdctoandh

I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. Relevant Skills and Experience FPGA/VHDL/Verilog/Zynq Proposed Milestones More

$1500 USD in 20 days
(55 Reviews)
5.6
vinodluhar

Hi I am working on Verilog-VHDL and Xilinx and altera tools and FPGAs by more that 3 years. I have implemented a similar project as you requires. I used virtex 7,(vc707 evaluation board) for my project. I had to acquir More

$1500 USD in 10 days
(3 Reviews)
3.8
punamsengupta

A proposal has not yet been provided

$750 USD in 25 days
(12 Reviews)
3.9
$1250 USD in 20 days
(6 Reviews)
3.0
$1250 USD in 10 days
(2 Reviews)
1.9
$1500 USD in 20 days
(0 Reviews)
0.0
kalshareef

I have been working with ZYNQ FPGA for a while and I have a good understanding of the UDP protocol so I am confident that I can get the job done. Looking forward working with you. Relevant Skills and Experience Have b More

$1222 USD in 20 days
(0 Reviews)
0.0