I have two tiny tasks : 1 - BCD up counter mod 60 with asynchronous reset and synchronous load.
2 - 8-bit shift register(shifting right?) asynchronous reset, 2 serial input( input right abd input left)and parallel output.
Fresher in VLSI industry with not many years of experience but a keen interest to explore and deliver.
Languages: Verilog, SystemVerilog, Perl, Python, TCL, C
Tools (Synthesis): Synopsys Design Compiler