Create a FSM to perform a filter

Closed Posted 2 years ago Paid on delivery
Closed Paid on delivery

I need help to Create a FSM to perform a filter. I will share more details in chat.

Verilog / VHDL

Project ID: #29920399

About the project

4 proposals Remote project Active 2 years ago

4 freelancers are bidding on average $66 for this job

moaazkh96

hi, I am a senior digital design engineer, I have a wide knowledge in digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE and Quartise. I will provide you a professional report about y More

$67 USD in 10 days
(24 Reviews)
4.5
LoganathanN

Hello team. We have seen your requirement is that you need help with Filtering with FSM. I’m an industrial expert. So I can do this job with the details. We have enough experience in MATLAB as well as digital design More

$67 USD in 1 day
(14 Reviews)
4.5
athulb

hii, im FPGA designer. i can write the fsm and make completely synthesiable code please contact me for further discussion

$65 USD in 3 days
(7 Reviews)
3.1
cbharathi258

Hello, I’m a digital design engineer with 3 yeara experience in digital design, verilog and systemverilog. I’ve also worked in MATLAB. I’ve recently completed a project on CIC filters in verilog. Depending on the compl More

$65 USD in 10 days
(0 Reviews)
0.0