OPTIMIZATION OF PLACEMENT AND ROUTING IN ASIC DESIGN

With the increased functionalities to be embedded, complexity of an IC has increased drastically. There was a time when some thousands of transistors used to suffice the expected functionality. But today those numbers have increased to millions and it's growing with the time. With the growth of transistors requirements, the expected size of ic is also becoming smaller. These transitions have made placement and routing as a prime focus for research communities. Meanwhile, deep learning has extended its realm and found its applications in IC designing for efficient optimization techniques. The optimization challenges involved with the placement and routing are minimization of wirelength, satisfying timing and power constraints, achieving 100% routability and avoiding congestion with increase in the complexity (especially while using 10+ metal layers). In ASIC designs, the placement of logical blocks and their connectivity impacts the performance of the design such as power and area requirements. Different optimization approaches using simulated annealing, quadratic SA, min-cut, genetic algorithms, nearest neighbourhood, discrete state transition etc. have been proposed and analysed, but an efficient approach is still unveiled. The proposed work will focus on experimental analysis of different optimization techniques and will develop an efficient optimization approach by incorporating deep-learning techniques. The proposed work will address the issue of congestion and total routability along with achieving the defined speed of design within the provided power requirement. Objectives: 1. To carry out the literature survey on available optimization techniques for placement and routing. 2. To deduce specifications and perform comparative analysis on the identified approaches 3. To develop an optimization model for placement and routing of ASIC design 4. To analyse the performance of the developed optimization model 5. To verify the developed optimization model using EDA tool highlighting the area cost, congestion, power and speed To tell as simple as possible I need a work that can be a algorithm or design, on any tool related to Optimization of placement and Routing for 1. The reduction of Wire Length. 2. Reduction of Area. 3. Increase Execution time.