4 bit signed carry adder

Dear sir I have more than 7 years experience in digital design using vhdl and verilog I will deliver you the design and testing bench

Sir, we are a group of Electrical Engineers with 5 years of experience. Please consider our services. Quality is our Guarantee. Regards

I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 8 years experience in digital design and well acquainted with ISE, NCverilog, Vivado 2013.4, EDK embedded tools & worked on Virtex-6 ML605, Virtex-5 LX110T, Virtex-4 ML401 , Spartan6, Spartan 3E, SOC Znyq Zedboard and MicroZed boards. I have completed 1G data traffic project where in-depth IEEE Ethernet 802.3 packet parsing is done according to rule set defined for voice & data packets. Each TCP, UDP and SIP packet is processing and transmits to destination and vice versa at receiving end. Xilinx Ethernet core is used only for capturing of packet from FPGA. Recently for client I have completed task where matrix multiplication is implemented using Vhdl. The matrix data were stored in ROM, by using address translation each row & column data is extracted and accumulated in multiply & add unit (MACU). After accumulation result is stored in RAM. I can do this project as I have carry look ahead completed. I am free can start work immediately and can work upto 40 hrs per week. Further we can discuss it and I look forward to receiving your response. Regard Mahar

Hello! I can deliver the solution for you in Verilog or VHDL in 1 day. Regards, Botond

i am willing to this project simple project module adder_4(a,b,cin,s,cout); input[3:0] a,b; input cin; output[3:0] s; output cout; wire c1, c2, c3; FullAdder fa0(a[0], b[0], cin, c1, s[0]); FullAdder fa1(a[1], b[1], cin, c1, s[1]); FullAdder fa2(a[2], b[2], cin, c1, s[2]); FullAdder fa3(a[3], b[3], cin, c1, s[3]); endmodule

I have more than 5 years experience in RTL coding using verilog HDL. It is an easy task and I will do it in 1 day. I need a good review on freelancer money is not my priority. I can help you on your project, you help me on freelancer

I have great experience in Verilog coding. I have finished many digital designs by using Verilog language, including a small CPU, 1080p video input & output, SHA256 algorithm. All these designs are synthesizable. Some of them even have been taped out. According to your attached files, this seems to be an easy task. I am able to finish it in one day. I plan to use Synopsys VCS simulator to generate output waveform in fsdb or vcd format.

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I have written a ARM7 compatible microprocessor with a 3 stage pipeline in Verilog during Graduation. So I am most suited for this project.

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Hello... I can do this for you..It is an easy assignment. Message me for the further details. Many thanks...

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I taught VHDL in college and this was one of the more common assignments, relatively simple as far as the coding is concerned the difficulty lies in the understanding of the circuits ... Currently, I'm a design engineer using Verilog daily, so this should be simple.