A Simple State Machine including Test bench

$30-250 AUD

Closed

Posted

about 12 years ago

$30-250 AUD

Paid on delivery

A Simple State Machine including Test bench Implement a simple state machine that controls the sequencing of the line LdA, LdB and LdS.Â The objective is to enable each of these at successive clock cycles such that you are able to load register A in cycle 1, then B in cycle 2 and to examine the result in cycle 3.Â See the timing diagram below.Â Use this template as a guide to setting up the FSM.Â There are more examples available for the FSM structure here.

Verilog / VHDL

Project ID: 1579936

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14 proposals

Remote project

Active 12 yrs ago

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14 freelancers are bidding on average $36 AUD for this job

@ahmedmohamed85

Dear sir, I can do this task

$50 AUD in 1 day

5.0

(304 reviews)

7.6

@ee4raja

Hi, I have 4.4 years of experience in VLSI domain design, verification and implementation. I can complete your project on time. Looking forward for your reply.

$30 AUD in 1 day

4.7

(8 reviews)

3.9

@PrinceJion

I am Electronics engineer and having experience in FPGA and verilog i can do it and we can discuss it in detail as well.

$30 AUD in 1 day

4.2

(1 review)

2.1

@hdlveca

I can do it.

$60 AUD in 3 days

5.0

(1 review)

1.8

@MuhammadSaeed786

as we agreed in PM

$30 AUD in 2 days

0.0

(0 reviews)

0.0

@VasileToma

Hi there - this is simple as it gets, one day one project done (will write-it in verilog, and guarantee to work with Modelsim and Ncsim) . Creers! -V.

$30 AUD in 1 day

0.0

(0 reviews)

0.0

@ExpertDigital

Hi, I am an experienced ASIC/FPGA designer. I have 10 years experience with VHDL and can accomplish your project within an hour.

$30 AUD in 1 day

0.0

(0 reviews)

0.0

@ccayaban

Hi Employer, I have 10 years experience in VHDL coding and prefer behavioral coding using finite state machines.I can finish the project in one day along with the testbench and the output waveforms.

$30 AUD in 1 day

0.0

(0 reviews)

0.0

@nklancer

Hi, Glad to meet you... I can able to give you the code. So, kindly consider my work. Thanking you.

$30 AUD in 1 day

0.0

(0 reviews)

0.0

@manzoor698

i will do this job for free of cost, kindly send the timing diagram

$30 AUD in 1 day

0.0

(0 reviews)

0.0

@DigitalProdigy

Hi A computer system engineer by profession, i am involved in many R&D projects. The posted project is simple and i can deliver code in verilog, plus a testbench and synthesized in xilinx for the fpga of ur choice, please contact for further details. Thanks n regards DP

$50 AUD in 10 days