Hi, I want to undertake your interesting project. I am a professional Verilog HDL (and VHDL) developer with 15+ years of experience. I have implemented and delivered quite a few projects, such as processor designs, custom controllers, FFTs and signal processing projects and so on. I understand that you want both designs (the BCD-to-excess3 and register file) implemented as part of the project. Quality work guaranteed, I will also include self-checking testbenches that run automatic diagnostics for simulation pass/fail. Of course you can always inspect waveform data and will provide the writeup as requested in the assignments' descriptions.