CPLD/FPGA VHDL/Verilog project

Circuit design for Lattice CPLD/MachXO. VHDL or Verilog. Interface to the Netburner processor module (see MOD5282). Timers. Encoders input processing. Counters. Pulse Width measurement. Ouput Compare Triggers. 32Bit Multiply and Shift operations. State Machine. We will submit more details upon acceptance. Duration 30 Days max. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Lattice CPLD MachXO family. Lattice compiler. The program can be compiled by the programmer on his own environment, I can do the final compilation with assistance until the porting to the lattice environment works.