Envelope detection using hilbert transform on FPGA

Dear sir I checked the attached link and i can do the design, please message me so that we can discuss more details Best regards

Greetings, I have good expertise with DSP, Matlab, HDL (VHDL & Verilog), FPGA programming. Please see my profile for details. I can assist you in this project. Look forward to hear from you.

Hello

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction. CSI-2 transmitter and receiver(6months) The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards eMMC Host Controller and Device controller(3months) The project is to develop eMMC host and Device controller IP according to the JEDEC standards. Mobile camera–testing(3months) The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies High resolution camera(6.5months) The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor -Test project for DDR2 accesses -Development of calibration module -Development of chain control module -Development of control signal generator -Development of Generic LUT module -Development of Divider radix-2 algorithm -Development of atan calculator -Development of MCB reader state machine Color Pipeline(15months) The project is to develop 2D and 3D image processing algorithms on Aptina sensor -Development of Generic Frame Buffer pCore -Development of data compression and data packing pCore -Development of data packing pCore Video Processing Unit(13 months) -Improvement in algorithms to reduce FPGA resource utilization and decrease latency

Hi I am Electrical Engineer and have done many freelancing projects. I am interested in doing your project. Hope we will be having discussion soon.

A proposal has not yet been provided

Several years of signal processing experience HDL coder experience for 5+ years; involvement in 100+ delivered projects for asic implementation

I am AbdulRahman, I have more than five years experience in HDL design using Verilog/VHDL. I made a lot of filter design using Verilog and VHDL. I can do the task in professional way. I just need to know the coefficients of the filter. The fixed point of the design then we can start.

As a computing engineer I have worked and been influenced with the filter algorithm. I have found some similar points on this project with my previous project on implementing text to speech system which I had used the filter to synthesize speech on FPGA.