Design Digital clock using VHDL

I've done it before for a customer, just send me the message and I give you the full code and guideline with the deal of 25$.

Dear sir I have more than 7 years experience in digital design using vhdl, I will provide you with unique code and I will explain everything thing to you in details

Hello! I can deliver the project for you in Quartus II. The current version I have installed in v13, that supports cyclone II. I start working as you select me as project provider. I deliver the quartus project as you created a milestone payment for the bid amount. Regards, Botond

Hi I have previous experience in digital clock , in verilog/vhdl both with the same Altera DE2 board itself. please let me know how to take this further ? Thanks Shobhit

Hello! I can help you right away! .

Hi I am an Electrical Engineer with lots of experience in digital circuit design and simulations using Hardware Descriptive Languages. I have used tools like Xilinx ISE etc for digital systems design. I assure you quality work with in time. Please check for my past projects. If you find me eligible for the task please contact. Thanks for reading. Regards

A proposal has not yet been provided

I am Computer and Telecommunication Engineering Student at the best technical university in Sri Lanka University of Moratuwa. I have completed few IC design modules. I know to write test benches as well. synthesis using snopsys IC compiler.... Lets do this.

I can help you. i have experience in this filed from last many years. i have designed many games and research project.

Hi, I am a professional developer, having lot of experience using VHDL. I can do this task easily. I want to discuss it with you. Regards Khizar.

I already did this project using Altera DE1 Board. So i need little time to finish this project. I will give you document/PPT about the code

Hi I am an Electrical Engineer with Computer as my specialization. I have experience in designing digital circuit using Hardware Descriptive Languages and their simulations using different tools like Xilinx ISE etc. Digital clock design seems to me a simple task. I assure you quality work with in time. Please reply so that we can share more information about the project. Thanks for taking time and reading. Regards Mohsin

Greetings. I have a simple explanation for why you should give me this project. "Because I already have made it during the third year of my graduation" The project is same, not a bit different. So I can deliver you the project within a day without any hassle. Thanks and regards

hi i am a post graduate in technology, have my graduation in electronics and communication engineering and mastered in electronics with specialization in VLSI and Embedded system. Have worked with VHDL and FPGAs some of my projects are >High Performance Hardware Implementation of Advanced Encryption Standard in FPGA >Synthesizable RTL Model of I2C Bus Controller using VHDL it will be my pleasure if we could work together on this project. looking forward... Arun Raju V K

Looking forward to work with you. You won't regret working with me. Thanks in advance. Syed Ali Nayyar Nasir

i will complete it because i work on vlog..............................................................................

A proposal has not yet been provided

Hi. Placed bid is for clock which use LCD, if you want just 7-segment display for clock then terms: $40/1 day.

I have an experience in writing VHDL code in my bachelors. In fact I had written the VHDL code of counters for the FPGA board of Xilinx in 2009.

l have done similar projects before on Xilinx spartan3 Start-Kit. There has a small liquid crystal panel which can display few black/white characters on it. l think its very similar to your project, the only thing is how accurate the presented hours and minutes, this is desided by the accuracy of the erternal oscillator.

I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset Characterization of FPGA”. In addition I had a one year experience to work with Physical Research Laboratory (PRL), Ahmadabad. In PRL I was working on Chandrayan-2 payload design where I had developed a DAQ for X- Ray florescence for elemental analysis. I had also made a project for Face Recognizance Using PCA in MATLAB. Please send me the details of your project. Currently I am also processing the data of dosimeter UDOS001 using Sparten-3E FPGA and onboard histogram generation using Sparten-3E FPGA with internal memory and external memory. I had already implemented the same using Sparten 3E. Please let me know the detail of your project.