Cadence software expert needed!

1. The project requires one to design a logic circuit in Cadence. The logic circuit will implement a combination of the SABL and TPDL logic styles. Simulation and analysis on the various parameters of the circuit are required as well. 2. I am currently finishing up my fourth year of electrical engineering at Carleton U. I have 2+ years of experience in designing logic circuits with MOSFETS and have implemented some different logic styles, including SABL and TPDL, through lab work and course material. So I have a very strong grasp of how logic gates work in terms of MOSFETS acting as switches, etc. 3. I will require at least a week to finish this logic circuit design, since I have other school work to do as well. 4. i) What sort of unbalanced conditions are you referring to? Do you mean timing conditions? ii) Exactly what parameters do you want analyzed and reported on? iii) When do you need this logic design to be completed?

Verilog/VHDL expert. I have had more than 4 years experiences on FPGA Design using Verilog and VHDL, Circuit design Multisim, Protues, PCB layout, MIPS Assembly, LogiSim, Simulink: - FPGA's Xilinx and Altera. - MicroBlaze, Embedded system design on FPGA of Xilinx. - FPGA, VLSI Implementation of DSP System( Matlab or C, C++, algorithm). - Digital logic design. - Some previous projects: + Matlab and FPGA Implementation of a License Plate Recognition System on FPGA Spartan-6 of Xilinx. + FPGA Implementation of a Fall Detection System on Virtex-5 Xilinx FPGA. + FPGA Implementation of a Fingerprint Identification System on Virtex-5 Xilinx FPGA. + VLSI Implementation of image/video compression in wavelet domain using DWT and SPIHT algorithm + Penalty football game on VGA DE2-70, DE2 Altera + AES 128, 256, 192. + MIPS Single-cycle, Pipeline processor