Vhdl programming matlab jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    1,780 vhdl programming matlab jobs found, pricing in NZD

    Implement a UDP communication protocol in VHDL to transmit and receive UDP packets. A linux based PC will send a UDP packet of arbitrary size over ethernet and zedboard FPGA should receive and do a logic operation on data and send back a packet of a different size back to the PC. Design also requires interfacing with the PHY chip on zedboard. Important

    $44 - $364
    $44 - $364
    0 bids

    Need to develop a very simple game using VHDL, to be run on an Altera DE1-SoC FPGA board. The game will use as external 4x4 keypad which will be connected to the board via one of the GPIO ports on the board. Also the game will use some 7-segment displays on the board to display some information regarding the game. The game itself is quite simple and

    $515 (Avg Bid)
    $515 Avg Bid
    5 bids

    FPGA IMPLEMENTATION VHDL CODE USING ALGORITHMS OF GA, AND CONTROL UNIT SYSTEM

    $231 (Avg Bid)
    $231 Avg Bid
    4 bids

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.

    $237 (Avg Bid)
    $237 Avg Bid
    10 bids

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    $291 (Avg Bid)
    $291 Avg Bid
    1 bids

    hey, I saw your work on the vhdl fm radio and I want to know if you're willing to send that same project.

    $218 (Avg Bid)
    $218 Avg Bid
    1 bids

    Need a vhdl project on mips pipelined processor

    $207 (Avg Bid)
    $207 Avg Bid
    9 bids

    We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.

    $58 / hr (Avg Bid)
    $58 / hr Avg Bid
    8 bids

    FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design

    $151 (Avg Bid)
    $151 Avg Bid
    7 bids

    The brightness measurement with help of PMODALS sensor ([login to view URL] one of the push buttons, the display should change between the display modes percent (0% -100%) and ADC value (0-255). I can send to you all necessary vhdl files for mc8051. Keywords: VHDL, C, SPI, mc8051, Basys3, FPGA, Ambient light sensor

    $324 (Avg Bid)
    $324 Avg Bid
    6 bids

    Hi Jin, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $233 (Avg Bid)
    $233 Avg Bid
    1 bids

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $291 (Avg Bid)
    $291 Avg Bid
    1 bids

    Hi Ahmed, I noticed your work on VHDL/FPGA related projects from your bio. I was wondering if you would like to work on a small project that is based on a FIFO implementation of a FM radio in VHDL. A C++ version of the code is already written, as well as a FIFO and Divider helper files in VHDL. We can discuss any details over chat.

    $233 (Avg Bid)
    $233 Avg Bid
    1 bids

    ...simple/minimal implementation using logic primitives (basic gates and flip flops). Secondly you are to produce a (more) fully capable design using VHDL. Both designs are to be verified by simulation. 6- The VHDL-based design should also be programmed into the FPGA on the development board and verified using the encoder hardware provided. More detailed specifications

    $596 (Avg Bid)
    $596 Avg Bid
    13 bids

    I have a VHDL source for the Altera EP3C25F256C8 FPGA design. I like an expert to setup the timing and fitting parameters to give the design optimum performance. I use Quartus II software version 8.1

    $410 (Avg Bid)
    $410 Avg Bid
    7 bids

    The distance measurement with help of MB1010 ultrasonic distance sensor ( https://www.maxbotix.co...displays. Pressing a button on the board should switch between inches, meters and centimeters. I can send to you all necessary vhdl files for mc8051. Keywords: Basys3, FPGA, Ultrasonic distance sensor, UART, mc8051 IP Core, VHDL, C, Vivado, ModelSim

    $396 (Avg Bid)
    $396 Avg Bid
    2 bids

    Hi Loi L., I noticed your previous work on the FIFO implementation of a FM Radio in VHDL. I was wondering if you would like to work on that same project. We can discuss any details over chat.

    $218 (Avg Bid)
    $218 Avg Bid
    1 bids

    The details of the design will be sent and discussed later. The freelancer needs to have proficient knowledge of VHDL and digital design. Only serious and professional freelancers needed

    $38 (Avg Bid)
    $38 Avg Bid
    4 bids

    I NEED VLSI CODE VHDL-7-5-Reed-Solomon ENCODER AND DECODER I HAVE SOME CODE JUST NEED TO RUN AND EXPLAIN MAKING SOME CORRECTIONS

    $23 (Avg Bid)
    $23 Avg Bid
    4 bids

    The brightness measurement with help of PMODALS sensor ([login to view URL] )...buttons the display should change between the display modes percent (0% -100%) and ADC value (0-255). I can send to you all necessary vhdl files for mc8051. Keywords: Basys3, FPGA, Ambient light sensor, SPI, mc8051, VHDL, C, Vivado

    $262 (Avg Bid)
    $262 Avg Bid
    9 bids

    In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. The VGA controller should be able to display images with a resolution of 640X480 pixels. Furthermore, it should be possible to select between two different images, depending on the position of switch SW1. Document description of whole design including images explanation of Testbench with...

    $160 (Avg Bid)
    $160 Avg Bid
    2 bids

    Hi, we have project for creating simple RISC processor through vhdl/Verilog. If interested will give more information

    $15 / hr (Avg Bid)
    $15 / hr Avg Bid
    1 bids

    VHDL/Verilog basic RISC Processor, will give more details if interested

    $10 / hr (Avg Bid)
    $10 / hr Avg Bid
    1 bids

    Hi, I need SPI master design in vhdl. Here is the data sheet. What I need is the functionality to read and write to SPI flash that is in the attached datasheet. I will give you $100 for it if you can successfully complete the project.

    $145 (Avg Bid)
    $145 Avg Bid
    1 bids

    Milestone 3: Digital Modulator, Error Block and Digital Demodulator Information often has to be transmitted from one location to another such that it is correctly received despite being sent through a noisy environment that could introduce errors. To achieve this a Digital Modulation Scheme can be used where specific modulation I & Q waveforms are then used to represent each of the four possib...

    $224 (Avg Bid)
    $224 Avg Bid
    4 bids

    I need a detailed video tutorial which includes the following material: - A tho...Generator" and 3. showing the results on the oscilloscope. The video tutorial should be at least 1 hour. All files and scripts should be shared. The project should be done in VHDL code. The whole procedure must be done in details and questions must be answered clearly.

    $353 (Avg Bid)
    NDA
    $353 Avg Bid
    5 bids

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    $60 (Avg Bid)
    $60 Avg Bid
    6 bids

    General Information “Counter Unit”, “IO Control Unit”, “Top Level & Testbench” and “Synthesis & Implementation will give you additional information about each sub-module of the project in order to realize the counter. FOR ALL DETAILS PLEASE CHECK DIGITAL DESIGN. pdf !!! Functional Specification A four-digit counter shall be implemented for the Ba...

    $71 (Avg Bid)
    $71 Avg Bid
    9 bids

    Here projects are implemented in VHDL programming using Xilinx software. B.E/[login to view URL] Mtech projects would include the kit implementation which can be done on sparten series based on the various application. Major projects and mini projects in VLSI for ECE students are done here.

    $196 (Avg Bid)
    $196 Avg Bid
    5 bids

    Vivado 2016.1 will be used. Create a testbench and simulate it in ModelSim with the help of the already provided script files. Design a synchronous system in VHDL which controls a two-storied elevator (ground floor and first floor). You will implement it with a two-process FSM as described above. The clock signal has a frequency of 10 MHz. The circuit

    $63 (Avg Bid)
    $63 Avg Bid
    11 bids

    ...this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and

    $41 (Avg Bid)
    $41 Avg Bid
    11 bids

    You have to programming a stopwatch with an Memory function in VHDL. It has to run on a Nexy 4 - fpga Board. Best regards, Kevin

    $279 (Avg Bid)
    $279 Avg Bid
    5 bids

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    $913 (Avg Bid)
    $913 Avg Bid
    23 bids

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $2457 (Avg Bid)
    $2457 Avg Bid
    8 bids

    ...nice and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and

    $1860 (Avg Bid)
    $1860 Avg Bid
    13 bids

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    $1091 (Avg Bid)
    $1091 Avg Bid
    1 bids

    ...be provided + timing chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information

    $1129 (Avg Bid)
    $1129 Avg Bid
    9 bids

    Looking for vhdl expert for Blockchain field. It must familiar with python too. Will give more detail via interview.

    $388 (Avg Bid)
    $388 Avg Bid
    6 bids

    Looking for an experienced programmer in Lattice FPGA's, specifically the ICE40 series. Simple project, buffer 320 bytes of data with multiple clock domains. Prefer VHDL

    $129 (Avg Bid)
    $129 Avg Bid
    7 bids

    I have a VHDL code. Then It has some issue. I need to fix it within a few hours. If you are electronic expert you can do it within 1 hours. I'll send details via interviewing. Ivan.

    $81 (Avg Bid)
    $81 Avg Bid
    10 bids

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

    $26 (Avg Bid)
    $26 Avg Bid
    1 bids
    $33 Avg Bid
    2 bids

    ...• Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

    $244 (Avg Bid)
    $244 Avg Bid
    3 bids

    Bug-fix Mining App and FPGA-VHDL Project. You have to fix the mining App what is written in C and running on a Linux server. And fix on the FPGA side the PLL and add multicores.

    $881 (Avg Bid)
    $881 Avg Bid
    6 bids

    I would like to implement a calculator which takes inputs from the ps2 keyboard and displays them on 7 segment.

    $84 (Avg Bid)
    $84 Avg Bid
    5 bids

    Tutor/Mentor Required(Online): -- Good knowledge of Embedded c/c++ and VHDL -- Good Experience with Renesas Microcontrollers and e2 Studio

    $10 / hr (Avg Bid)
    $10 / hr Avg Bid
    9 bids

    Muktiplexer of 2 to 1 in vhdl using tje software xillinix

    $29 (Avg Bid)
    $29 Avg Bid
    3 bids

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    $81 (Avg Bid)
    $81 Avg Bid
    24 bids

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [login to view URL]; a. The source can

    $909 (Avg Bid)
    $909 Avg Bid
    3 bids

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    $672 (Avg Bid)
    $672 Avg Bid
    10 bids